Timing or counting system

ABSTRACT

A timing or counting system of the purely electronic type which may be used with 50 or 60 Hz-voltages. As a timer, it is regulated by the cycles of the line. It can also time from 10 milliseconds to 11/2 hours. Manually settable digital switches are associated with the present circuit to enable selection of a predetermined decimal count or timing interval. The input line frequency (60 cycles) is doubled, then divided by a number of frequency dividing circuits. A clock pulse generator feeds clock pulses via Schmidt triggers and logic circuits to a read-only memory which controls the operation of the dividers. A special decoding circuit operates to convert to a decimal form the output of one of the dividers associated with the decimal switch for the least significant place.

[ Apr. 8, 1975 41 TIMING OR COUNTING SYSTEM [75] Inventor: Grover K.Houpt, Wayne. Pa.

[73] Assignee: American Manufacturing Company,

Inc., King of Prussia. Pa.

[22] Filed: Oct. 31, 1973 [21] Appl. No.: 411,230

Related US. Application Data [63] Continuation of Ser. No. 248,632.April 28 1972 235/92 CA; 58/23 R, 23 A; 324/181. 186'. 307/226; 328/48[56] References Cited UNITED STATES PATENTS 3.662.330 5/1972 Meredith328/48 3.684.870 8/1972 Nelson 3.762.152 10/1973 Marz ..58/23R +12DECODER Primary E.\'aminerGareth D. Shaw Assistant E.\'uminer.loseph M.Thesz, Jr. Attorney. Agent, or Firm-Maleson, Kimmelman & Ratner [57]ABSTRACT A timing or counting system of the purely electronic type whichmay be used with 50 or 60 Hz-voltages. As a timer, it is regulated bythe cycles of the line. It can also time from 10 milliseconds to 1 /2hours. Manually settable digital switches are associated with thepresent circuit to enable selection of a predetermined decimal count ortiming interval. The input line frequency (60 cycles) is doubled, thendivided by a number of frequency dividing circuits. A clock pulsegenerator feeds clock pulses via Schmidt triggers and logic circuits toa read-only memory which controls the operation of the dividers. Aspecial decoding circuit operates to convert to a decimal form theoutput of one of the dividers associated with the decimal switch for theleast significant place.

4 Claims, 2 Drawing Figures PATENTEDAPR 8191s SHEET 2 0F 2 l0 coLOTIMING OR COUNTING SYSTEM This is a continuation application of Ser. No.248,632, filed Apr. 28, 1972 now abandoned.

I BACKGROUND OF THE INVENTION 1. Field of the Invention The inventionrelates to counters or timers of the purely electronic type. As a timer,it relates to those monitored by the cycles of the supply linealternating current.

2. Prior Art Electro mechanical timers and counters have limited rangesand/or resolution. This is also true of electronic timers whichincorporate a resistance-capacitance circuit as the primary timingcircuit. Therefore, to cover a wide range these former systems requiredthe use of many different timers and dials, which is not onlyinconvenient for the user but entails more expensive productioninvestment on the part of the manufacturer. Furthermore, as a result ofthe inter-relation of the var ious mechanical parts the life expectancyof electro mechanical timers left something to be desired. It was alsonecessary with electro mechanical timers to change the driving motors ifthe timers were to be operated on 50 Hz as opposed to 60 Hz.

While there did exist in the prior art timers having digital settingcapability, the timing resolution of these timers was somewhat limited.

The objects of the present invention therefore include the provision ofa purely electronic timer or counter whose life expectancy is determinedprimarily by' the life of the output relay with which it is customarilyused. Also, a simple plug-in change converts its operation from 50 Hz to60 Hz, and-vice versa. Its resolution is considerably better thanelectro mechanical types because essentially every cycle of the linevoltage is counted inythe timing mode. The present invention also doesnot require expensive, fast-operating circuits to drive the counters init, as is the case with other timers or counters employing MOS. Thepresent invention also provides a much greater range capability thanpreviously was available.

BRIEF SUMMARY OF THE INVENTION A timing (or counting) circuit which ismanually settable to a predetermined digital timing (or counting)setting. Means are provided for dividing the frequency of the line toproduce counting pulses supplied to the various decades feeding thedecimal digital setting switches. This means includes means for dividinga multiple of the line frequency and decoding the quotient so as toprovide signals corresponding to the ten possible settings of thedigital switch associated with the least significant place.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are schematic andpartially block diagrams of the timing or counting systems according tothe present invention.

DETAILED DESCRIPTION OF THE DRAWINGS Overall Summary of Componentsgenerator (which does not include resistor R5) shown within another suchrectangle B and a clock pulse generator shown in rectangle C. Aplurality of manuallysettable digital switches 55 is shown in stillanother broken-line rectangle D, which are connected to an MOSintegrated circuit 30. The power supply A furnishes filtered DC to allof the other components. The reset pulse generator B readies thecircuits on the MOS 30 for the beginning of a cycle of operation. Theclock pulse generator C supplies clock pulses to the circuits on theintegrated circuit 30 at a rate determined by the frequency of the ACline. The manually-settable decimal digital switches 55 are set by theoperator of the timing (or counting) circuit according to apredetermined time lapse, interval or count. When set, they determinethe time-lapse cycle interval or counting operation of the integratedcircuit 30 to which they are connected. l/C 30 divides the clock pulsesand counts them until the setting of the digital switches is matched,whereupon the cycle is completed. Plug-socket assembly PL 1 enables theoperator to choose timing either by minutes or by seconds. Plug-socketassembly PL 2 permits the operator to set the timer for operation fromthe standard -cycle line or a SO-cycle line.

Operation Reset and Enabling Counting When switch SW1 is closed, linevoltage is supplied to input terminals 1 and 2 at 50 cycles or 60 cyclesas the case may be. If it is 60 cycles, the assembly PL2 is set asshown; if 50 cycles, the plug is moved to the 50 cycle socket. Whenpower is supplied by throwing the switch SW1, the power supply A isturned on but requires a finite time to reach its steady-statecondition. As the voltage builds up across Cl, transistor O1 is renderedconductive and voltage is applied to terminal 21 through resistors R3and R4. The Zener diode CR3 prior to achievement of the steady statecondition is not conductive, there is no voltage across R11, andconsequently transistor O2 is off. The voltage applied via R3 and R4 toterminal 21 of I/C 30 is a logic 1 and is transmitted via bufferamplifier 42 to-ROM terminal c. The ROM is structured so that the pulsewhich emerges from terminalfis a logic 0 and is applied throughinverting amplifier 49 as a logic I to set all of the counters on l/C 30to zero.

When capacitor C l charges to a predetermined voltage, the Zener diodeCR3 in parallel with it conducts so that there is current throughresistor R11 and out of the base of PNP transistor Q2, turning thelatter on. When this happens, the voltage at the terminal 21 effectivelygoes to a logic 0" (zero or ground) which is transferred through bufferamplifier 42 to the terminal 0 of the ROM 50. As a result, due to thecircuit characteristics of the ROM, terminal f of the ROM 50 goes to lwhich, when transmitted via the inverting amplifier 49 as a 0,conditions the counters 33, 35, 36, 37, and

. 38 to accept counts at their respective inputs.

Operation Clock Pulse Generation System The clock generator C isconnected via input terminals 53 and 54 to the regular 60 Hertz AC line.It includes a full-wave rectifier bridge CR2 which supplies a Hz wave tothe base of transistor Q3 when the circuit is operated as a timer. Thisturns the transistor on and off at a 120 Hertz rate. The collector of O3is connected through R5 to the regulated 27 V. at the emitter of Q1 andtherefore the collector of Q3 swings between 27V. (logic l andapproximately zero volts at a 120 Hz. rate. This 120 Hz. clamped voltagewave is applied to the input terminal 19 of 1/C 30 which is connected toan inverting Schmidt trigger circuit 39 that inverts the input signal.

Ordinarily, very fast circuits are required to drive counters, but suchfast-acting circuits are susceptible to noise since noise spikes may beelectrically indistinguishable from the output pulses since they bothhave fast rise and fall times. By using Schmidt trigger circuits on the1/C 30, the use of fast driving circuits off the l/C 30 are obviated.When the slow-rise 120 Hz. pulses are applied to the input of theSchmidt trigger 39, the latter produces inverted rectangular 120 Hz.pulses having very sharp leading and trailing edges. These pulses areeventually applied to the counters 33, 35, etc., when the circuit isused for a timing operation, via gates 45 48. When the circuit is usedfor counting, these gates determine the polarity of the signal appliedto the counters. 1n the timing operation, the 120 Hz rectangular pulsesare applied to one input of NOR circuit 46 as well as to one input ofAND circuit 45. At the same time, there is applied to the other inputsof NOR circuit 46 and AND circuit 45 a constant 27 volt l signal fromthe emitter of Q1 (which has been rendered conductive) via terminal 18and buffer amplifier 40. When the input to one terminal of AND circuit45 is a l, the output will be a replica of the input to its otherterminal.

The NOR circuit 46 will have a logic output that is applied to one inputof NOR gate 47. To the other input of the same gate there will beapplied the output signal from AND gate 45 so that the output of NORgate 47 will be an inversion of the output of gate 45. The output waveof gate 47 is applied to one input of NOR gate 48 together with a signalfrom the e terminal of the ROM 50. If this signal is a 0, the 120 cycleclock pulse train is passed by gate 48 onto the input of frequencydivider 33. If the signal at the output terminal e is a l there is nooutput from NOR gate 48 and counting is thereby disabled.

When the circuit is used to count, assembly PL3 may be alternativelyconnected so that the plug is grounded, i.e., a 0", rather than pluggedinto 27 volts (1). In this hook-up, Os will be applied via terminal 18to gates 45 and 46 so that the pulses to be counted will have theirpolarity reversed.

Operation Frequency Dividing Circuits The divider 33 is conditioned todivide by 60 only when there is a l at terminal 17 and a 1 at ROMterminal f. A l at terminal 17 is passed via buffer amplifier 31 to thedivider 33 when the plug of plug- I The output of the divider 33 isapplied to one input of the dual-mode divider 35. This divider iscapable of dividing, depending'upon its input control signal, either by10 or by 12. When PL2 is connected for 60-cyc1e operation as shown, thecounter 35 will divide by 12 since there is applied to its other input avia buffer amplifier 32 from the 27 volt line connected to the emitterof Q1. The same 1 is also applied to one input of the decoder 34.

The divider 35, since it has divided the pulses per minute by 12, willproduce and apply to divider 36 10 pulses per minute. Divider 36 willtherefore produce and apply to divider 37 one pulse per minute. Divider37 will therefore produce and apply to divider 38 one pulse per each 10minutes. The divider 38 has no carry output.

It is seen that the dividers 36, 37 and 38 each produce four-bit binaryoutputs that are connected through buffer amplifiers 52 to contacts ofthe manually settable decimal digital switches. Divider 38 is connectedto contacts which when manually set by manipulation of the digit wheelsrepresent l0s. Dividers 37 and 36 are connected to switches 55 that areoperated by digit wheels representing, respectively, ones and tens.

It may thus be seen that the maximum range from the counter will be99.99 minutes when the plug-socket PL-l is connected as shown. 1fit'were connected so that the plug was in the seconds socket, therewould be a 0 at terminal 17 which would, when applied to the divider 33,disable the division by 60. Therefore, instead of two pulses out of thedivider 33 per second there would be 120 pulses out per second. However,since the other dividers 35, 36, 37, and 38 would function the same, themaximum count would then be 99.99 seconds. The digital switchesrespectively close or open a set of four contacts for each decimalnumeral visible to the operator.

The divider 35, however, is not directly connected to four switchesrepresenting binary digital places corresponding to hundredths. Rather,the divider 35 is connected through a decoder 34 and four bufferamplifiers to one set of contacts.

Operation Decoder 34 9 on the digital switch representing thehundredths.-

Using the decoder 34 constructed to operate according to the followingTruth Table (Table 1) gives a maximum error less than 0.003.

Carry propagate output to counter 36.

The Output B column of the above table is applicable only to operationwhen the divider 35 is operative in the divide by twelve modecorresponding to operation of the timer on 60 cycles and the setting ofthe plugsocket PL-Z as shown. The Output F column is applicable for 50cycle operation or for use of the circuit in the counting mode. Byreference to Table 1, it isseen that the inputs to the decoder 34 arethe same as the outputs therefrom when the count is 0, 1 and 2. When thecount at the input to the decoder is 3, the output count is 2. When thecounts at the input are 4, 5, 6 and 7 respectively, the outputs lagbehind, being 3, 4, 5 and 6 respectively. When the count at the input is'8 or 9, the count at the output is 7 in both instances. When the countat the input is 10 and 11, the output count is 8 and 9 respectively.When the count is 12, the outputs are the same (i.e., zero) and this isa recycle or carry count.

Thus, twice during the count two successive input digits result in thesame output digit. This happens for input digits 2 and 3 which result inoutput digit 2, and input digits 8 and 9 which result in output digits7. Consequently, even though 120 pulses per second are applied todivider 35, only 10 different digital output signals resultcorresponding to the 10 different possible settings of the associateddigit wheels.

Each of the buffer amplifers 52 has a low resistance to ground, whichact as means for comparing the outputs of the counters (or decoder 34)with the settings of the switches 55, for a logic and a high resistancefor a logic 1. For example, if the timer is set to time out at onesecond operating at 60 cycles per second, all of the switches 55 will beopen except switch 55 i. The plug of assembly PL-l will be put into theseconds socket so that terminal 17 will be grounded and therefore a 0will appear at it. If the plug in PL2 is in the 60 cycles position,terminal 26 will be at 27 volts (a logic 1 so that the buffer amplifier32 applies a 1 to decoder 34 and divider 35. When timing is started byclosure of the switch SW1, capacitor C1 begins to charge and power isapplied to the reset pulse generator B. The reset pulse generatorfunctions as previously explained to set all the counters to 0 andthereafter, after the Zener diode CR3 conduct all the counters and othercircuits of the l/C 30 are enabled to begin count- TABLE 2 InputsOutputs Inputs Outputs abcd efg abcd efg 0000 011 0001 010 1000 110 1001000 0100 010 0101 011 1100 111 1101 110 0010 001 0011 001 TABLE2-Continued Inputs Outputs Inputs Outputs I010 001 101 l 001 01 1O 001O] l l OOI l l 10 001 1 l l 1 001 With the starting condition as statedabove for input terminals a, b, c and d, it is seen that the outputterminals e,f, g are at 0, l, and 1. Since the terminal e is at 0, theNOR circuit 48 permits the 120 Hertz signal to be applied to the divider33 and counting may begin. The 1 appearing at the terminal f is invertedto 0 by the inverting buffer amplifier 49 so that when applied to thedividers 33, 35, 36, 37 and 38 they are not reset. The l at terminal gis inverted by buffer amplifier 51 so that a 0 is applied to transistorQ4 and renders it non-conductive so that output relay coil RL-2 is notenergized. Since the terminal 17 is at 0, the divider 33 is enabled tobegin counting by ones the Hz wave at the output of NOR circuit 48..These same pulses are applied to divider 35 which is linked to divider36 and counting at their respective inputs proceeds-The timing operationcontinues until the first carry" pulse isissued by divider 36. Thisproduces a signal in the output line of divider 37 corresponding to theleast significant binary place. This output line is connected to thebuffer amplifier 52i that is connected to the digital switch 55i. Untilthis happens, all of the bus 60 is at ground potential. As soon asamplifier 52i receives the 1 signal, it becomes non-grounded and the bus60 goes to 27 volts. This makes terminal a of ROM 50 go to a logic 1.Thus, the terminals of the ROM are then as follows:

d=l Therefore, the output terminals are as follows:

When this happens, relay coil RL2 is actuated and the timing cycle, isterminated. Simultaneously, the timing operation is disabled by theapplication of a 1 from terminal e to one input of NOR gate 48 whichthereupon blocks passage of the 120 Hz signalthrough it. However, thereset is not activated because the 1 on terminal f is inverted byinverting amplifier 49 to a 0. Opening switch SW1 deenergizes the relaycompleting the cycle.

General Comments When the circuit is used for counting, the clock pulsegenerator C is disconnected and, instead, the pulses to be counted areapplied to terminal 19 of I/C 30. If the setting of plug-socket assemblyPL 3 is as shown in FIG. 1, the signal applied to be counted at theinput to divider 33 will be reversed in polarity as compared with itsappearance at terminal 19. If the plug of that assem bly is connected toground, the signal at the input to divider 33 will have the samepolarity as it did at terminal 19.

When the circuit is operated as a timer with a 50 Hz line voltage, theassembly PL 2 is set with the plug grounded. This causes a 0 to appearat terminal 26 and this disables the decoder 34. That 0 will also causedivider 35 to operate in the divide by ten mode on the 100 Hz signalapplied to terminal 19.

In order to use the circuit for interval timing rather than for delayedtiming, the terminal 23 may be grounded instead of being connected to 27volts. If this is done, the relay coil RL 2 will be energized during thedesired interval, but not before and after.

The decimal binary switches 55 may be, for example, of the type shown inUS. Pat. No. 3,497,138 of Fisher or could be modifications of the wheelsshown in US. Pat. No. 3,100,299 issued to Congdon. Another suitable typeof switch is shown in the co-pending application of Donald H. Ross, Ser.No. 251,922, filed May 10, 1972, which is assigned to the same assigneeas this invention, and now abandoned.

I claim:

1. A timing or counting system comprising:

a. a source of an AC signal having a predetermined frequency,

b. a non-decimal modulus binary digital counting means to which saidsource frequency is applied,

c. a series of binary digital counting means to which 'said non-decimalmodulus counting means is coupled,

d. a plurality of sets of switching means coupled to a voltage sourceand being settable to a plurality of conditions in which they produceabinary signal corresponding to selected decimal numbers,

e. a plurality of variable conductive means respectively coupled to saidsets of switching means,

f. conversion means coupled to said non-decimal I modulus counter and tothe one of said sets of switching means associated with the counting ofthe least significant figure of a selected decimal number, saidconversion means converting the output binary count of said non-decimalmodulus counter to a binary number count having a decimal modulus, theothers of said sets of switching means being coupled to the series ofbinary counting means which are associated with the more significantfigures of said selected decimal number.

2. The system according to claim 1 wherein said (b) means includes ameans for dividing the frequency of the signal by 12 and wherein said(0) means includes a divider by 60 and a predetermined number ofdividers by 10, all of said dividers being serially connected.

3. A timing or counting system operable from an AC voltage sourcecomprising:

a. means for multiplying the frequency of said AC voltage,

b. a non-decimal modulus binary digital counting means to which saidfrequency-multiplied AC voltage is applied,

c. a series of binary digital counting means to which saidfirst-mentioned counting means is coupled,

d. a plurality of sets of switching means coupled to another voltagesource and being settable to a plurality of conditions in which theyproduce binary signals corresponding to selected decimal numbers,

e. a plurality of variable conductive means coupled to said sets ofswitching means,

f. conversion means coupled to said non-decimal modulus counter and tothe one of said sets of switching means associated with the counting ofthe least significant figure of a selected decimal number, saidconversion means converting the output binary count of said non-decimalmodulus counter to a binary number count having a decimal modulus, theothers of said ((1) means being coupled to the counters associated withthe more significant figures of said selected number.

4. The system according to claim 3 wherein said conversion means iscoupled to said one of said sets of switching means through the variableconductive means associated therewith and wherein the others of saidswitching means are coupled to their respective associated countersthrough corresponding associated ones of said variable conductive means.

1. A timing or counting system comprising: a. a source of an AC signalhaving a predetermined frequency, b. a non-decimal modulus binarydigital counting means to which said source frequency is applied, c. aseries of binary digital counting means to which said non-decimalmodulus counting means is coupled, d. a plurality of sets of switchingmeans coupled to a voltage source and being settable to a plurality ofconditions in which they produce a binary signal corresponding toselected decimal numbers, e. a plurality of variable conductive meansrespectively coupled to said sets of switching means, f. conversionmeans coupled to said non-decimal modulus counter and to the one of saidsets of switching means associated with the counting of the leastsignificant figure of a selected decimal number, said conversion meansconverting the output binary count of said nondecimal modulus counter toa binary number count having a decimal modulus, the others of said setsof switching means being coupled to the series of binary counting meanswhich are associated with the more significant figures of said selecteddecimal number.
 2. The system according to claim 1 wherein said (b)means includes a means for dividing the frequency of the signal by 12and wherein said (c) means includes a divider by 60 and a predeterminednumber of dividers by 10, all of said dividers being serially connected.3. A timing or counting system operable from an AC voltage sourcecomprising: a. means for multiplying the frequency of said AC voltage,b. a non-decimal modulus binary digital counting means to which saidfrequency-multiplied AC voltage is applied, c. a series of binarydigital counting means to which said first-mentioned counting means iscoupled, d. a plurality of sets of switching means coupled to anothervoltage source and being settable to a plurality of conditions in whichthey produce binary signals corresponding to selected decimal numbers,e. a plurality of variable conductive means coupled to said sets ofswitching means, f. conversion means coupled to said non-decimal moduluscounter and to the one of said sets of switching means associated withthe counting of the least significant figure of a selected decimalnumber, said conversion means converting the output binary count of saidnon-decimal modulus counter to a binary number count having a decimalmodulus, the others of said (d) means being coupled to the countersassociated with the more significant figures of said selected number. 4.The system according to claim 3 wherein said conversion means is coupledto said one of said sets of switching means through the variableconductive means associated therewith and wherein the others of saidswitching means are coupled to their respective associated countersthrough corresponding associated ones of said variable conductive means.